m_�R�� �����Ew�q���z-?�9�G�i-eXT�vV2/��Ÿ�uy\Q�����y����\��uUI֥,��*����0y��g�!��x�RD� b���˙��+ːͩŁ��~Y�I�ʝb5��L/yY��_����Q�����\2(>��.�^�RS����, ���8wu!���v�xx[O��c羱�x� b�I��C�m�M����aR,bD�BB����0� QQ��0*Vom��� In this article we will take an example of a very generic functional clocking architecture as shown in Figure 1 and modify it.
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Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 2 Overview Reading ... one of the safest clocking methods around, and the one we will use in this class.
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In stuck-at testing the frequency of the clock domain we will be testing doesn’t matter; but in at-speed testing, we should be testing the clock domain at the maximum frequency it supports because of the reason discussed here. 0000004154 00000 n The cloud like structures in the figure indicates different clock domains (having the logic we want to test). To prevent this, we need to add a simple mux as shown in Figure 4, which will mask the functional control in scan mode (Test Mode = 1), to select the clock with highest frequency (in this case the 200 MHz clock).
If we scan the divider, the logic responsible for dividing the clock will become part of scan chain and will toggle during scan mode, resulting in clock of unpredictable frequency at the output of divider; so we should not scan this divider.
VLSI-1 Class Notes Clocking Overhead per Technology Generation Clocking overhead ( skew and jitter ) is growing as we move to DSM processes. 0000013547 00000 n Clock mux – Maximum possible frequency at the output is 200 MHz. We have six clock domains, thus six OCCs.
DIV (2) – which divides the input clock by 2.
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The frequency shown in red inside the clock domains (cloud like structures) in Figure 4, indicates the maximum clock frequency of that clock domain. This reduces the clock skew between the reference chip and all other chips by as much as 50%. 0000000667 00000 n ‘DIV (1 or 4)’ – We need the undivided clock of 500 MHz (fastest clock), thus we need to mask the functional control to select the undivided clock in scan mode, as shown in Figure 3.
1.2. Since the FSM controlling the select pin of clock mux will be part of scan chains, it will toggle during testing. There is also a clock mux, which has a functional control that selects which clock it should propagate at its output. Now let us go through the modifications needed in clocking architecture for making the design ‘Scan’ friendly –. %PDF-1.2 %����
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